FSD124: GUI and Compiler function requirements, module tests and integration tests

Products	Safety Simplifier
Requirements	FSD114, FSD120
Purpose	GUI and Compiler function requirements, module tests and integration tests.
Input	FSD123, FSD121, FSD114, FSD120
Output
61508 Refs	61508-2 clause 7.2 - 7.7

Table of contents

Document Description

This document contains the requirement specifications, integration tests, and module tests for GUI function blocks and Compiler function blocks, according to FSD123: Function block development procedure.

To read the test results refer to the test results of FSD124 in pdf format: FSD124v10 results

Test setup and equipment

The different test setups are described in the appendix. Each test specifies the test setup, equipment, and software that is being used.

Software

Relevant software used is specified for each test. Firmware version is specified for both processors.

Equipment

• Power supply: Kiprim DC605S

• Oscilloscope: RIGOL DS1054Z

• Logic analyzer: Saleae Logic Pro (8/16)

• PC: Windows 11 64-bit

• Multimeter: UNI-T UT132E

• Multimeter: UNI-T UT33A

• Multimeter: Victor 70C

• Micro-USB cable

• USB type C cable

• 802.15.4 USB radio dongle

GUI function blocks

2.1 Single Input

Single Input requirements flow diagram

Market requirement: Function block: Single Input MREQ_SINGLE_INPUT

status: PASS tags: mreq, block, single_input Derived: HAZARD_SINGLE_INPUT_01

A Single Input function block shall be available to users in Simplifier Manager. The block should be able to configure a single pin as a digital input, and optionaly set specific or relative voltage thresholds. It may also be configured to use different signal types as ON/OFF (e.g. high/low voltage or X-pulses).

Hazard: Function block: Single Input HAZARD_SINGLE_INPUT_01

status: PASS tags: hazard, block, single_input Derived: SPEC_SINGLE_INPUT Source: MREQ_SINGLE_INPUT

If the voltage thresholds are not set correctly, the block may incorrectly identify the input signal as a high signal even if it should be low.

Hazard: Function block: Single Input HAZARD_SINGLE_INPUT_02

status: PASS tags: hazard, block, single_input Derived: SPEC_SINGLE_INPUT

If the block (due to a bug) uses the wrong pin, it may to the user seem like an input is working correctly, but it is measuring another pin.

Specification: Function block: Single Input SPEC_SINGLE_INPUT

status: PASS tags: spec, block, single_input Derived: TEST_SINGLE_INPUT_1, TEST_SINGLE_INPUT_2, TEST_SINGLE_INPUT_3 Source: HAZARD_SINGLE_INPUT_01, HAZARD_SINGLE_INPUT_02

The Single Input function block shall allow the user to configure a single input pin with optional voltage thresholds. Inputs None (in the actual block diagram). Outputs “on”: 1 when the input signal is above the high threshold, and 0 when it is below the low threshold. Properties pin number [1,16]: Which pin to use as input. OFF [0V, nX-pulse]: Which signal type to consider as OFF state. ON [VDC, X-pulse]: Which signal type to consider as ON state. Specific voltage thresholds can optionally be set for the ON and OFF states. If not set, the block should use the default thresholds for the specific signal type. The default is specified per node in the SL3 configuration file. Underlying Compiler Blocks To simplify the implementation in the compiler, two different blocks are created, depending on the signal type. dig_input: This block is used when the ON/OFF signal types are VDC/0V (i.e., standard digital input). pulse_input: This block is used when any signal type is X-pulse. Only one of these are used in the final SL3 code, depending on the configuration of the block.

2.1.2 Module tests

TEST: Single Input sl3 code review TEST_SINGLE_INPUT_1

status: PASS tags: single_input_test Derived: RESULT_SINGLE_INPUT_1 Source: SPEC_SINGLE_INPUT, SWSREQ_011A, SWSREQ_011B, SWSREQ_011C, SWSREQ_011D, SWSREQ_011E

Preconditions Generate a Single Input block with the on output connected to the input of any other block and the following properties: Pin = 1 OFF = 0V ON = VDC specific voltage thresholds not set Procedure Verify that the generated sl3 code contains a Single Input function with the correct inputs and output, according to the underlying compiler block spec. Verify that all input signals to the block are in the correct place in the sl3 output. Adjust the pin number to 2 and verify that the generated sl3 code is updated accordingly. Set the specific high and low voltage thresholds and verify that the generated sl3 code is updated accordingly. Set the ON/OFF signal types to different X-pulses and verify that the generated sl3 code uses the pulse_input block, and that the correct signal types are used.

2.1.3 Integration tests

TEST: Verify Single Input function TEST_SINGLE_INPUT_2

status: PASS tags: single_input_test Derived: RESULT_SINGLE_INPUT_2 Source: SPEC_SINGLE_INPUT, SWSREQ_015A

Preconditions Compile a Single Input connected to a Single Output and the following properties: Pin = 1 OFF = 0V ON = VDC default voltage thresholds Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output is LOW/OFF/0V. Apply a high signal to the input and verify that the output turns on within X ms of the high flank on the input. Vary the voltage of the input signal to below and above the low and high thresholds and verify that the output changes accordingly.

TEST: Single Input in safety manual TEST_SINGLE_INPUT_3

status: PASS tags: single_input_test Derived: RESULT_SINGLE_INPUT_3 Source: SPEC_SINGLE_INPUT

Verify that the safety aspects of the Single Input block are documented in the safety manual.

2.1.4 Test results

ID	Tags	Status
TEST_SINGLE_INPUT_1	single_input_test	PASS
TEST_SINGLE_INPUT_2	single_input_test	PASS
TEST_SINGLE_INPUT_3	single_input_test	PASS

2.2 Single Output

Single Output requirements flow diagram

Market requirement: Function block: Single Output GUI MREQ_SINGLE_OUTPUT

status: PASS tags: mreq, block, single_output Derived: HAZARD_SINGLE_OUTPUT_01

There shall exist a GUI function block that allows the user to configure a single output pin with optional voltage thresholds.

Hazard: Function block: Single Output GUI HAZARD_SINGLE_OUTPUT_01

status: PASS tags: hazard, block, single_output Derived: SPEC_SINGLE_OUTPUT Source: MREQ_SINGLE_OUTPUT

Safety relies on the Single Output GUI function block to correctly configure a single output pin with optional voltage thresholds. If the Single Output GUI function block is not functioning correctly, the output pin may not be configured correctly, which could lead to an unsafe function.

Specification: Function block: Single Output GUI SPEC_SINGLE_OUTPUT

status: PASS tags: spec, block, single_output Derived: TEST_SINGLE_OUTPUT_1, TEST_SINGLE_OUTPUT_2, TEST_SINGLE_OUTPUT_3 Source: HAZARD_SINGLE_OUTPUT_01

The Single Output GUI function block shall allow the user to configure a single output pin with optional voltage thresholds.

2.2.2 Module tests

TEST: Single Output sl3 code review TEST_SINGLE_OUTPUT_1

status: PASS tags: single_output_test Derived: RESULT_SINGLE_OUTPUT_1 Source: SPEC_SINGLE_OUTPUT, SWSREQ_011A, SWSREQ_011B, SWSREQ_011C

Preconditions Generate a Single Output block with one input. Procedure Verify that the generated sl3 code contains a Single Output function with the correct inputs and output. Verify that all input signals to the block are in the correct place in the sl3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the sl3 output.

2.2.3 Integration tests

TEST: Verify Single Output function TEST_SINGLE_OUTPUT_2

status: PASS tags: single_output_test Derived: RESULT_SINGLE_OUTPUT_2 Source: SPEC_SINGLE_OUTPUT, SWSREQ_015A

Preconditions Generate a Single Output block with one Single Input block connected to it. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the input signal is correctly mapped to the output signal.

TEST: Single Output in safety manual TEST_SINGLE_OUTPUT_3

status: PASS tags: single_output_test Derived: RESULT_SINGLE_OUTPUT_3 Source: SPEC_SINGLE_OUTPUT

Verify that the safety aspects of the Single Output block are documented in the safety manual.

2.2.4 Test results

ID	Tags	Status
TEST_SINGLE_OUTPUT_1	single_output_test	PASS
TEST_SINGLE_OUTPUT_2	single_output_test	PASS
TEST_SINGLE_OUTPUT_3	single_output_test	PASS

2.5 Advanced input

Inputs, outputs, and properties correspond to the underlying compiler function block inputs, outputs, and parameters respectively.

The safe compiler parameter is hard coded to be always true.

Note: In the compiler, setting the max_diff to 0 disables the simultaneity check, which means “no simultaneity” or “infinite simultaneity”. To a user however, setting the max_diff to 0 intuitively means the pins can never diff (all contacts must close at exactly the same time). To avoid misunderstanding, the Enable Simultaneity property is used to disable simultaneity on the GUI block, which sets the max_diff of the compiler block to 0. Enabling simultaneity allows the user to change the max_diff value

2.5.1 Requirement specification

Inputs

None

Outputs

• ON: Corresponds to the compiler block output “on”.

• ERROR: Corresponds to the compiler block output “error”.

Properties

• StartUp Test: Corresponds to the compiler block parameter startup_test.

• Filter ON (ms): Corresponds to the compiler block parameter debounce_on.

• Filter OFF (ms): Corresponds to the compiler block parameter debounce_off. If set to true, enables the Simultaneity (ms) property.

• Enable Simultaneity [true, false]: If set to false, disables the Simultaneity (ms) property and sets it to 0. If set to true, enables the Simultaneity (ms) property.

• Simultaneity (ms): Corresponds to the compiler block parameter max_diff. This property can be enabled and disabled by the Enable Simultaneity property

• OFF state min time (ms): Corresponds to the compiler block parameter req_all_zero.

• Terminal Count: Sets how many pins should be used in the function

• Terminal Properties:

  • Terminal Number

  • Signal Type ON

  • Signal Type OFF

  • Voltage High

  • Voltage Low

Underlying Compiler Blocks

2.5.2 Module tests

TEST: Advanced input module tests TEST_GUI_ADVANCED_INPUT_1

status: PASS Source: DREQ_26A, SWSREQ_011A, SWSREQ_011B, SWSREQ_011C, SWSREQ_011D, SWSREQ_011E, SWSREQ_012A, SWSREQ_014A

See FSD124 test results.

2.5.3 Integration tests

TEST: Advanced input integration tests TEST_GUI_ADVANCED_INPUT_2

status: PASS

See FSD124 test results.

2.6 Advanced output

Inputs, outputs, and properties correspond to the underlying compiler function block inputs, outputs, and parameters respectively.

2.6.1 Requirement specification

Inputs

• “ON”: Corresponds to the compiler input “on”.

• “ERROR reset (optional)”: Corresponds to the compiler input “error_reset”.

• “Feedback” (optional): Corresponds to the compiler input “allow_rise”.

Outputs

• “ERROR” (optional): Corresponds to the compiler output “error”.

Properties

• Enable ERROR Output: Enables the “ERROR” output.

• Enable ERROR Reset: Enables the “ERROR Reset” input.

• Enable Feedback: Enables the “Feedback” input.

• Terminal Count: Specifies how many pins should be used in the function.

• Terminal Properties:

  • Pin number

  • Signal Type ON

  • Signal Type OFF

  • Error Sets OFF

Underlying Compiler Blocks

Tests

TEST: Advanced output module tests TEST_GUI_ADVANCED_OUTPUT_1

status: PASS Source: SWSREQ_011A, SWSREQ_011B, SWSREQ_011C, SWSREQ_013A

See FSD124 test results.

2.7 Gate

Gate requirements flow diagram

Market requirement: Function block: Gate MREQ_GATE

status: PASS tags: mreq, block, gate Derived: SPEC_GATE

There shall exist a GUI function block that allows the user to configure a Gate block with a specified type of boolean operation [AND/NAND/OR/NOR/XOR/XNOR].

Specification: Function block: Gate SPEC_GATE

status: PASS tags: spec, block, gate Derived: TEST_GATE_1, TEST_GATE_2, TEST_GATE_3, TEST_GATE_4, TEST_GATE_5, TEST_GATE_6, TEST_GATE_7, TEST_GATE_8, TEST_GATE_9, TEST_GATE_10, TEST_GATE_11, TEST_GATE_12, TEST_GATE_13 Source: MREQ_GATE

The Gate function block shall allow the user to configure a gate block with a specified type of boolean operation. Inputs Configurable between 2-16. Outputs “”: The result of the operation. Parameters type [AND/NAND/OR/NOR/XOR/XNOR]: This parameter is used to select the type of gate. The Gate function block shall perform a specified boolean function on 2-16 input signals. The function to perform shall be selectable between AND, NAND, OR, NOR, XOR, and XNOR. Underlying Compiler Blocks Truth Tables AND Input 1 Input 2 Input 3 Output 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 NAND Input 1 Input 2 Input 3 Output 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 OR Input 1 Input 2 Input 3 Output 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 NOR Input 1 Input 2 Input 3 Output 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 XOR Input 1 Input 2 Input 3 Output 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 XNOR Input 1 Input 2 Input 3 Output 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0

2.7.2 Module tests

TEST: AND Gate sl3 code review TEST_GATE_1

status: PASS tags: gate_test Derived: RESULT_GATE_1 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: AND Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=and. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: NAND Gate sl3 code review TEST_GATE_2

status: PASS tags: gate_test Derived: RESULT_GATE_2 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: NAND Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=nand. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: OR Gate sl3 code review TEST_GATE_3

status: PASS tags: gate_test Derived: RESULT_GATE_3 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: OR Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=or. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: NOR Gate sl3 code review TEST_GATE_4

status: PASS tags: gate_test Derived: RESULT_GATE_4 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: NOR Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=nor. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: XOR Gate sl3 code review TEST_GATE_5

status: PASS tags: gate_test Derived: RESULT_GATE_5 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: XOR Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=xor. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: XNOR Gate sl3 code review TEST_GATE_6

status: PASS tags: gate_test Derived: RESULT_GATE_6 Source: SPEC_GATE

Preconditions Generate a Gate block with the following configuration in the GUI: Type: XNOR Inputs: 16 Procedure Verify that the generated SL3 code contains a gate function with type=xnor. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.7.3 Integration tests

TEST: Verify AND Gate function TEST_GATE_7

status: PASS tags: gate_test Derived: RESULT_GATE_7 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of an AND Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for an AND gate to verify the output is correct. Verify that the output is LOW/OFF/0V when all inputs are LOW/OFF/0V. Verify that the output is HIGH only when all 16 inputs are HIGH.

TEST: Verify NAND Gate function TEST_GATE_8

status: PASS tags: gate_test Derived: RESULT_GATE_8 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of a NAND Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for a NAND gate to verify the output is correct. Verify that the output is HIGH when all inputs are LOW/OFF/0V. Verify that the output is LOW only when all 16 inputs are HIGH.

TEST: Verify OR Gate function TEST_GATE_9

status: PASS tags: gate_test Derived: RESULT_GATE_9 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of an OR Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for an OR gate to verify the output is correct. Verify that the output is LOW/OFF/0V when all inputs are LOW/OFF/0V. Verify that the output is HIGH when any input is HIGH.

TEST: Verify NOR Gate function TEST_GATE_10

status: PASS tags: gate_test Derived: RESULT_GATE_10 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of a NOR Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for a NOR gate to verify the output is correct. Verify that the output is HIGH when all inputs are LOW/OFF/0V. Verify that the output is LOW only when any input is HIGH.

TEST: Verify XOR Gate function TEST_GATE_11

status: PASS tags: gate_test Derived: RESULT_GATE_11 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of an XOR Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for an XOR gate to verify the output is correct. Verify that the output is LOW/OFF/0V when all inputs are LOW/OFF/0V. Verify that the output is HIGH only when an odd number of inputs are HIGH.

TEST: Verify XNOR Gate function TEST_GATE_12

status: PASS tags: gate_test Derived: RESULT_GATE_12 Source: SPEC_GATE

Preconditions Compile 16 single input blocks connected to the inputs of an XNOR Gate block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Use the truth table for an XNOR gate to verify the output is correct. Verify that the output is HIGH when all inputs are LOW/OFF/0V. Verify that the output is HIGH only when an even number of inputs are HIGH or all inputs are LOW/OFF/0V.

TEST: Gate in safety manual TEST_GATE_13

status: PASS tags: gate_test Derived: RESULT_GATE_13 Source: SPEC_GATE

Verify that the safety aspects of the Gate block are documented in the safety manual.

2.7.4 Test results

ID	Tags	Status
TEST_GATE_1	gate_test	PASS
TEST_GATE_2	gate_test	PASS
TEST_GATE_3	gate_test	PASS
TEST_GATE_4	gate_test	PASS
TEST_GATE_5	gate_test	PASS
TEST_GATE_6	gate_test	PASS
TEST_GATE_7	gate_test	PASS
TEST_GATE_8	gate_test	PASS
TEST_GATE_9	gate_test	PASS
TEST_GATE_10	gate_test	PASS
TEST_GATE_11	gate_test	PASS
TEST_GATE_12	gate_test	PASS
TEST_GATE_13	gate_test	PASS

2.8 NOT

NOT requirements flow diagram

Market requirement: Function block: NOT MREQ_GUI_NOT

status: PASS tags: mreq, block, not Derived: SPEC_GUI_NOT

A NOT function block shall be available to users in Simplifier Manager.

Specification: Function block: NOT SPEC_GUI_NOT

status: PASS tags: spec, block, not Derived: TEST_NOT_1, TEST_NOT_2, TEST_NOT_3 Source: MREQ_GUI_NOT

The NOT function block shall perform a logical negation of the input signal. The NOT function block shall have one input and one output. The NOT function block shall invert the input signal to produce the output signal. Inputs “input”: Corresponds to the compiler function input “input”. Outputs output: Corresponds to the compiler function output “”. Properties None Underlying Compiler Blocks

2.8.2 Module tests

TEST: NOT sl3 code review TEST_NOT_1

status: PASS tags: not_test Derived: RESULT_NOT_1 Source: SPEC_GUI_NOT

Preconditions Generate a NOT block with an input and an output. Procedure Verify that the generated sl3 code contains a NOT function with the correct input and output. Verify that all input signals to the block are in the correct place in the sl3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the sl3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other sl3 parameters).

2.8.3 Integration tests

TEST: Verify NOT block functionality with various inputs TEST_NOT_2

status: PASS tags: not_test Derived: RESULT_NOT_2 Source: SPEC_GUI_NOT

Preconditions Compile a NOT block with a Single Input block connected to the input and a Single Output block connected to the output. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the input signal is correctly inverted to the output signal. Repeat the test with various input signals (high/low) and verify that the output is inverted within an acceptable timeframe.

TEST: NOT in safety manual TEST_NOT_3

status: PASS tags: not_test Derived: RESULT_NOT_3 Source: SPEC_GUI_NOT

Verify that the safety aspects of the NOT block are documented in the safety manual.

2.8.4 Test results

ID	Tags	Status
TEST_NOT_1	not_test	PASS
TEST_NOT_2	not_test	PASS
TEST_NOT_3	not_test	PASS

2.9 SR Latch

SR Latch requirements flow diagram

Market requirement: Function block: SR-latch MREQ_BLOCK_SR_LATCH

status: PASS tags: mreq, block, sr_latch Derived: HAZARD_BLOCK_SR_LATCH

An SR-latch function shall be available to users in Simplifier Manager.

Hazard: Function block: SR-latch HAZARD_BLOCK_SR_LATCH

status: PASS tags: hazard, block, sr_latch Derived: SPEC_BLOCK_SR_LATCH Source: MREQ_BLOCK_SR_LATCH

A general SR-latch function has undefined behavior when both inputs are high. This can lead to undefined behavior in the system.

Specification: Function block: SR-latch SPEC_BLOCK_SR_LATCH

status: PASS tags: spec, block, sr_latch Derived: TEST_SR_LATCH_1, TEST_SR_LATCH_2, TEST_SR_LATCH_3 Source: HAZARD_BLOCK_SR_LATCH

The SR-latch block performs a general SR-latch function: When the S input is 1, the output Q shall be 1. When the R input is 1, the output Q shall be 0. When both inputs are 0, the output shall retain its previous state. When both inputs are simultaneously 1, the output shall be 0. Inputs S: A 1 on this input sets the output Q to 1. R: A 1 on this input sets the output Q to 0. Outputs Q: The latch output. Properties None Compiler blocks Maps 1:1 to the compiler block 3.5 latch_sr.

2.9.2 Module tests

TEST: SR-Latch sl3 code review TEST_SR_LATCH_1

status: PASS tags: sr_latch_test Derived: RESULT_SR_LATCH_1 Source: SPEC_BLOCK_SR_LATCH

Preconditions Compile an SR Latch block with all inputs and outputs connected to other function blocks. Procedure Verify that the generated sl3 code contains an SR Latch function with the correct inputs and output. Verify that all input signals to the block are in the correct place in the sl3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the sl3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other sl3 parameters).

2.9.3 Integration tests

TEST: Verify SR Latch function TEST_SR_LATCH_2

status: PASS tags: sr_latch_test Derived: RESULT_SR_LATCH_2 Source: SPEC_BLOCK_SR_LATCH

Preconditions Compile two single input blocks connected to the S and R inputs of an SR Latch block, and the Q output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output is LOW/OFF/0V. Apply a high signal pulse to the S input and verify that the output turns on within X ms of the high flank on the S input. Apply a high signal pulse to the R input and verify that the output turns off within X ms of the high flank on the R input. Apply a high signal to both the S and R inputs and verify that the output is off.

TEST: SR-Latch in safety manual TEST_SR_LATCH_3

status: PASS tags: sr_latch_test Derived: RESULT_SR_LATCH_3 Source: SPEC_BLOCK_SR_LATCH

Verify that the safety aspects of the SR-latch block are documented in the safety manual.

2.9.4 Test results

ID	Tags	Status
TEST_SR_LATCH_1	sr_latch_test	PASS
TEST_SR_LATCH_2	sr_latch_test	PASS
TEST_SR_LATCH_3	sr_latch_test	PASS

2.10 Toggle Latch

Toggle Latch requirements flow diagram

Market requirement: Function block: Toggle Latch MREQ_BLOCK_T_LATCH

status: PASS tags: mreq, block, toggle_latch Derived: SPEC_BLOCK_T_LATCH

A Toggle Latch function shall be available to users in Simplifier Manager.

Specification: Function block: Toggle Latch SPEC_BLOCK_T_LATCH

status: PASS tags: spec, block, t_latch Derived: TEST_T_LATCH_1, TEST_T_LATCH_2, TEST_T_LATCH_3 Source: MREQ_BLOCK_T_LATCH

The Toggle Latch block performs a general toggle latch function: When the T input receives a high flank signal the output Q shall toggle between 0 and 1. Inputs T: A high signal flank on this input toggles the output Q. Outputs Q: The latch output. Properties None Syntax: var.my_t_latch = latch_tog(var.toggle)

2.10.2 Module tests

TEST: T-Latch sl3 code review TEST_T_LATCH_1

status: PASS tags: t_latch_test Derived: RESULT_T_LATCH_1 Source: SPEC_BLOCK_T_LATCH

Preconditions Generate a Toggle Latch block with all inputs and outputs connected to other function blocks. Procedure Verify that the generated sl3 code contains a Toggle Latch function with the correct inputs and output. Verify that all input signals to the block are in the correct place in the sl3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the sl3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other sl3 parameters).

2.10.3 Integration tests

TEST: Verify T Latch function TEST_T_LATCH_2

status: PASS tags: t_latch_test Derived: RESULT_T_LATCH_2 Source: SPEC_BLOCK_T_LATCH

Preconditions Compile a single input block connected to the T input of a Toggle Latch block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output is LOW/OFF/0V. Apply a high signal to the T input and verify that the output toggles within X ms of the high flank on the T input. Repeat this test multiple times to verify that the output toggles within X ms every time the T input receives a high signal.

TEST: T-Latch in safety manual TEST_T_LATCH_3

status: PASS tags: t_latch_test Derived: RESULT_T_LATCH_3 Source: SPEC_BLOCK_T_LATCH

Verify that the safety aspects of the T-latch block are documented in the safety manual.

2.10.4 Test results

ID	Tags	Status
TEST_T_LATCH_1	t_latch_test	PASS
TEST_T_LATCH_2	t_latch_test	PASS
TEST_T_LATCH_3	t_latch_test	PASS

2.11 D Latch

D Latch requirements flow diagram

Market requirement: Function block: D Latch MREQ_BLOCK_D_LATCH

status: PASS tags: mreq, block, d_latch Derived: SPEC_BLOCK_D_LATCH

A D Latch function shall be available to users in Simplifier Manager.

Specification: Function block: D Latch SPEC_BLOCK_D_LATCH

status: PASS tags: spec, block, d_latch Derived: TEST_D_LATCH_1, TEST_D_LATCH_2, TEST_D_LATCH_3 Source: MREQ_BLOCK_D_LATCH

The D Latch block performs a general D latch function: When the E input is high, the output Q shall store the input D. When the E input is low, the output Q shall remain the same even if the input D changes. Inputs D: The input data. E: The enable signal. Outputs Q: The latch output. Properties None

2.11.2 Module tests

TEST: D-Latch sl3 code review TEST_D_LATCH_1

status: PASS tags: d_latch_test Derived: RESULT_D_LATCH_1 Source: SPEC_BLOCK_D_LATCH

Preconditions Generate a D Latch block with all inputs and outputs connected to other function blocks. Procedure Verify that the generated sl3 code contains a D Latch function with the correct inputs and output. Verify that all input signals to the block are in the correct place in the sl3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the sl3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other sl3 parameters).

2.11.3 Integration tests

TEST: Verify D Latch function TEST_D_LATCH_2

status: PASS tags: d_latch_test Derived: RESULT_D_LATCH_2 Source: SPEC_BLOCK_D_LATCH

Preconditions Compile 2 single input blocks connected to the D and E inputs of a D Latch block, and the output connected to a single output block. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output is LOW/OFF/0V. Give a high signal to the D input and confirm that the output is not changed. Give a high signal to the E input and give a high signal to the D input. Confirm that the output changes to the value of the D input when the E input is high. Give a low signal to the E input and confirm that the output is saved and remains the same even if the D input changes.

TEST: D-Latch in safety manual TEST_D_LATCH_3

status: PASS tags: d_latch_test Derived: RESULT_D_LATCH_3 Source: SPEC_BLOCK_D_LATCH

Verify that the safety aspects of the D-latch block are documented in the safety manual.

2.11.4 Test results

ID	Tags	Status
TEST_D_LATCH_1	d_latch_test	PASS
TEST_D_LATCH_2	d_latch_test	PASS
TEST_D_LATCH_3	d_latch_test	PASS

2.12 Sync inputs

There shall exist a GUI function block that allows the user to configure a sync inputs block. This function is useful for applications where multiple signals need to be synchronized, such as two-hand control devices.

Inputs, outputs, and properties correspond to the underlying compiler function block inputs, outputs, and parameters respectively.

• The Sync Inputs function block shall have configurable inputs between 2-16.

• The Sync Inputs function block shall ensure that all inputs are in a consistent state before transitioning to the ON state.

2.12.1 Requirement specification

Inputs

• Configurable between 2-16.

Outputs

• “on”: This output is 1 if the function is in the ON state.

Parameters

• Startup-test [true/false]: Maps to startup_test in the compiler block. If true, the function starts in the WAIT_FOR_OFF(OFF) state at the time of power on. If false, the function starts in the OFF state at the time of power on.

• Filter ON [0-10000ms]: Maps to debounce_on in the compiler block. The function will wait this time when an input goes to 1, before considering that input to be 1. If the input goes back to 0, the time is reset.

• Filter OFF [0-10000ms]: Maps to debounce_off in the compiler block. The function will wait this time when an input goes from 1 to 0 before considering that input to be 0. If the input goes back to 1 before the given time, the time is reset.

• OFF state min time [0-10000ms]: Maps to req_all_zero in the compiler block. The function requires all inputs to be 0 for at least this time before it can go to ON state again.

• Simultaneity [0-10000ms]: Maps to simultaneity in the compiler block. When the function is going from OFF to ON state, the inputs can differ for at most this time. If they differ for more than this time, the function will go to ERROR state and require a new valid OFF state, before it can go to ON state again.

2.12.2 Module tests

ID	Tags	Status
TEST_GUI_SYNC_INPUTS_1	sync_inputs_gui_module_tests	PASS
TEST_GUI_SYNC_INPUTS_2	sync_inputs_gui_module_tests	PASS
TEST_GUI_SYNC_INPUTS_3	sync_inputs_gui_module_tests	PASS

TEST: Sync inputs: req_zero_time = 0, simultaneity = 0, debounce_on = 0, debounce_off = 0, startup_test = True TEST_GUI_SYNC_INPUTS_1

status: PASS tags: sync_inputs_gui_module_tests Derived: RESULT_GUI_SYNC_INPUTS_1 Source: DREQ_26A, SWSREQ_017A

Test specification Compile a Sync inputs block with the following parameters: req_zero_time = 0, simultaneity = 0, debounce_on = 0, debounce_off = 0, startup_test = True. Pass Criteria Verify that the generated c code contains a sync_inputs function with a req_zero_time of 0, simultaneity of 0, debounce_on of 0, debounce_off of 0 and a startup_test of True. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Sync inputs: req_zero_time = 10000, simultaneity = 10000, debounce_on = 10000, debounce_off = 10000, startup_test = True TEST_GUI_SYNC_INPUTS_2

status: PASS tags: sync_inputs_gui_module_tests Derived: RESULT_GUI_SYNC_INPUTS_2 Source: DREQ_26A

Test specification Compile a Sync inputs block with the following parameters: req_zero_time = 10000, simultaneity = 10000, debounce_on = 10000, debounce_off = 10000, startup_test = True. Pass Criteria Verify that the generated c code contains a sync_inputs function with a req_zero_time of 10000, simultaneity of 10000, debounce_on of 10000, debounce_off of 10000 and a startup_test of True. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Sync inputs: req_zero_time = 1, simultaneity = 2, debounce_on = 3, debounce_off = 4, startup_test = False TEST_GUI_SYNC_INPUTS_3

status: PASS tags: sync_inputs_gui_module_tests Derived: RESULT_GUI_SYNC_INPUTS_3

Test specification Compile a Sync inputs block with the following parameters: req_zero_time = 1, simultaneity = 2, debounce_on = 3, debounce_off = 4, startup_test = False. Pass Criteria Verify that the generated c code contains a sync_inputs function with a req_zero_time of 1, simultaneity of 2, debounce_on of 3, debounce_off of 4 and a startup_test of False. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.12.3 Integration tests

Test result summary

ID	Tags	Status
TEST_GUI_SYNC_INPUTS_4	sync_inputs_gui_integration_tests	PASS
TEST_GUI_SYNC_INPUTS_5	sync_inputs_gui_integration_tests	PASS
TEST_GUI_SYNC_INPUTS_6	sync_inputs_gui_integration_tests	PASS
TEST_GUI_SYNC_INPUTS_7	sync_inputs_gui_integration_tests	PASS
TEST_GUI_SYNC_INPUTS_8	sync_inputs_gui_integration_tests	PASS

TEST: Sync inputs: Default values TEST_GUI_SYNC_INPUTS_4

status: PASS tags: sync_inputs_gui_integration_tests Derived: RESULT_GUI_SYNC_INPUTS_4

Test Input Compile and download a Sync inputs block connected with 2 inputs and 1 output to a node. Pass Criteria Verify that the generated c code contains a sync_inputs function with the correct inputs and outputs. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Sync inputs: Minimum values TEST_GUI_SYNC_INPUTS_5

status: PASS tags: sync_inputs_gui_integration_tests Derived: RESULT_GUI_SYNC_INPUTS_5

Test Input Compile and download a Sync inputs block with the minimum values for all parameters. Pass Criteria Verify that the generated c code contains a sync_inputs function with the correct inputs and outputs for minimum values. Verify that all input signals to the block are in the correct place in the SL3 output for minimum values. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output for minimum values. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters) for minimum values.

TEST: Sync inputs: Maximum values TEST_GUI_SYNC_INPUTS_6

status: PASS tags: sync_inputs_gui_integration_tests Derived: RESULT_GUI_SYNC_INPUTS_6

Test Input Compile and download a Sync inputs block with the maximum values for all parameters. Pass Criteria Verify that the generated c code contains a sync_inputs function with the correct inputs and outputs for maximum values. Verify that all input signals to the block are in the correct place in the SL3 output for maximum values. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output for maximum values. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters) for maximum values.

TEST: Sync inputs: Simultaneous changes TEST_GUI_SYNC_INPUTS_7

status: PASS tags: sync_inputs_gui_integration_tests Derived: RESULT_GUI_SYNC_INPUTS_7

Test Input Compile and download a Sync inputs block with simultaneous changes in multiple inputs. Pass Criteria Verify that the generated c code contains a sync_inputs function with the correct inputs and outputs for simultaneous changes. Verify that all input signals to the block are in the correct place in the SL3 output for simultaneous changes. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output for simultaneous changes. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters) for simultaneous changes.

TEST: Sync inputs: Timing verification TEST_GUI_SYNC_INPUTS_8

status: PASS tags: sync_inputs_gui_integration_tests Derived: RESULT_GUI_SYNC_INPUTS_8

Test Input Compile and download a Sync inputs block and perform timing verification using an oscilloscope or logic analyzer. Pass Criteria Verify that the timing behavior of the generated c code matches the expected behavior. Verify that all input signals to the block are in the correct place in the SL3 output for timing verification. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output for timing verification. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters) for timing verification.

2.13 Square wave

Filter requirements flow diagram

Market requirement: Function block: Square wave MREQ_BLOCK_SQUARE_WAVE

status: PASS tags: mreq, block, square_wave Derived: SPEC_BLOCK_SQUARE_WAVE

A Square wave function shall be available to users in Simplifier Manager.

Specification: Function block: Square wave SPEC_BLOCK_SQUARE_WAVE

status: PASS tags: spec, block, square_wave Derived: TEST_SQUARE_WAVE_1, TEST_SQUARE_WAVE_2, TEST_SQUARE_WAVE_3, TEST_SQUARE_WAVE_4, TEST_SQUARE_WAVE_5 Source: MREQ_BLOCK_SQUARE_WAVE

The Square Wave function block shall generate a square wave signal based on the specified high and low times. The Square Wave function block shall have a start value that determines the initial state of the output signal. The Square Wave function block shall have an enable input that can start and stop the square wave signal. Inputs “enable”: When = 1 starts the square wave. Maps to ctrl in the compiler block. Outputs “output”: This output produces the square wave function. Parameters High Time [1-10000 ms]: Maps to t_on in the compiler block. The time in milliseconds the output is 1. Low Time [1-10000 ms]: Maps to t_off in the compiler block. The time in milliseconds the output is 0. Start Value [0-10000 ms]: Maps to start_val in the compiler block. The time in milliseconds the output is 0 before the first cycle. #SEARCH REPLACE

2.13.2 Module tests

TEST: Square wave sl3 code review TEST_SQUARE_WAVE_1

status: PASS tags: sqrwave_test Derived: RESULT_SQUARE_WAVE_1 Source: SPEC_BLOCK_SQUARE_WAVE

Preconditions Compile a Square wave block with the following parameters: High Time = 1 ms, Low Time = 2 ms, Start Value = 3 ms. Procedure Verify that the generated c code contains a sqrwave function with a t_on of 1 ms, t_off of 2 ms, and a start_val of 3 ms. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Square wave: Min values TEST_SQUARE_WAVE_2

status: PASS tags: sqrwave_test Derived: RESULT_SQUARE_WAVE_2 Source: SPEC_BLOCK_SQUARE_WAVE

Preconditions Compile a Square wave block with the following parameters: High Time = 1 ms, Low Time = 1 ms, Start Value = 0 ms. Procedure Verify that the generated c code contains a sqrwave function with a t_on of 1 ms, t_off of 1 ms, and a start_val of 0 ms. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Square wave: Max values TEST_SQUARE_WAVE_3

status: PASS tags: sqrwave_test Derived: RESULT_SQUARE_WAVE_3 Source: SPEC_BLOCK_SQUARE_WAVE

Preconditions Compile a Square wave block with the following parameters: High Time = 10000 ms, Low Time = 10000 ms, Start Value = 10000 ms. Procedure Verify that the generated c code contains a sqrwave function with a t_on of 10000 ms, t_off of 10000 ms, and a start_val of 10000 ms. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.13.3 Integration tests

TEST: Verify Square Wave function TEST_SQUARE_WAVE_4

status: PASS tags: sqrwave_test Derived: RESULT_SQUARE_WAVE_4 Source: SPEC_BLOCK_SQUARE_WAVE

Preconditions Compile a Square Wave function block connected to one single output. Download to a single unit and measure the output with a logic analyzer or oscilloscope. Procedure Verify that the output signal is a square wave with the specified high and low times. Change the high and low times and verify that the output signal changes accordingly.

TEST: Square wave in safety manual TEST_SQUARE_WAVE_5

status: PASS tags: sqrwave_test Derived: RESULT_SQUARE_WAVE_5 Source: SPEC_BLOCK_SQUARE_WAVE

Verify that the safety aspects of the Square wave block are documented in the safety manual.

2.13.4 Test results

ID	Tags	Status
TEST_SQUARE_WAVE_1	sqrwave_test	PASS
TEST_SQUARE_WAVE_2	sqrwave_test	PASS
TEST_SQUARE_WAVE_3	sqrwave_test	PASS
TEST_SQUARE_WAVE_4	sqrwave_test	PASS
TEST_SQUARE_WAVE_5	sqrwave_test	PASS

2.14 Reset

Reset requirements flow diagram

Market requirement: Function block: Reset MREQ_RESET

status: PASS tags: mreq, block, reset Derived: SPEC_RESET

A Reset function block shall be available to users in Simplifier Manager.

Specification: Function block: Reset SPEC_RESET

status: PASS tags: spec, block, reset Derived: TEST_RESET_1, TEST_RESET_2, TEST_RESET_3, TEST_RESET_4, TEST_RESET_5, TEST_RESET_6 Source: MREQ_RESET

The Reset function block shall perform a reset operation on the input signal based on the reset signal and allow_reset signal. The Reset function block shall have three inputs and two outputs. The Reset function block shall ensure that the reset signal is valid by checking the time between the positive and negative edges of the reset input. Inputs “input”: The signal to apply the reset function to. “reset”: The signal that controls the reset functionality. “allow_reset”: A boolean signal that enables the reset functionality. Outputs “run”: The output signal that is controlled by the reset functionality. “lamp”: A visual indicator that reflects the reset process status. Parameters Minimum Push Time [0-10000 ms]: Maps to min_push_time in the compiler block. The minimum time the reset signal must be active before the output is reset. Underlying Compiler Blocks

2.14.2 Module tests

TEST: Reset: Minimum Push Time = 20 TEST_RESET_1

status: PASS tags: reset_test Derived: RESULT_RESET_1 Source: SPEC_RESET

Preconditions Compile a Reset block with the following parameters: Minimum Push Time = 20 ms, Allow Reset = True, Enable lamp output = True. Procedure Verify that the generated c code contains a reset function with a min_push_time of 20 ms and that the allow_reset and enable_lamp parameters are set to True. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Reset: Minimum Push Time = 0 TEST_RESET_2

status: PASS tags: reset_test Derived: RESULT_RESET_2 Source: SPEC_RESET

Preconditions Compile a Reset block with the following parameters: Minimum Push Time = 0 ms. Procedure Verify that the generated c code contains a reset function with a min_push_time of 0 ms. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Reset: Minimum Push Time = 10000 TEST_RESET_3

status: PASS tags: reset_test Derived: RESULT_RESET_3 Source: SPEC_RESET

Preconditions Compile a Reset block with the following parameters: Minimum Push Time = 10000 ms. Procedure Verify that the generated c code contains a reset function with a min_push_time of 10000 ms. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.14.3 Integration tests

TEST: Verify Reset function 1 TEST_RESET_4

status: PASS tags: reset_test Derived: RESULT_RESET_4 Source: SPEC_RESET

Preconditions Compile a Reset block with Single Input blocks connected to the inputs and a Single Output block connected to the output and the following parameters: Minimum Push Time = 100 ms Allow Reset = False Enable lamp output = False Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the run output is LOW/OFF/0V. Apply a high signal pulse longer than the minimum push time to the reset input and verify that the run output remains LOW/OFF/0V. While the reset input is low, apply a high signal to the input input and verify that the run output remains LOW/OFF/0V. Apply a high signal to the input input and apply a signal pulse longer than the minimum push time to the reset input and verify that the run output goes high. Reset the output to LOW/OFF/0V and repeat the previous step and apply a signal pulse shorter than the minimum push time to the reset input and verify that the run output remains LOW/OFF/0V.

TEST: Verify Reset function 2 TEST_RESET_5

status: PASS tags: reset_test Derived: RESULT_RESET_5 Source: SPEC_RESET

Preconditions Compile a Reset block with Single Input blocks connected to the inputs and a Single Output block connected to the output and the following parameters: Minimum Push Time = 100 ms Allow Reset = True Enable lamp output = True Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the run output is LOW/OFF/0V and that the lamp output is high. Apply high pulses to the input input and reset input and verify that the run output remains LOW/OFF/0V and the lamp output remains high. Apply a high singal to the allow_reset input. Apply a high signal pulse longer than the minimum push time to the reset input and verify that the run output remains LOW/OFF/0V and the lamp output remains high. Apply a high signal to the input input and verify that the run output remains LOW/OFF/0V and the lamp output generates a signal pulse. Apply a signal pulse longer than the minimum push time to the reset input and verify that the run output goes high and the lamp output goes low. Apply a low signal to the input input and then apply it a high signal to reset the test. Repeat step 6 but with a signal pulse shorter than the minimum push time and verify that the run output remains LOW/OFF/0V and the lamp output is genereating a signal pulse.

TEST: Reset in safety manual TEST_RESET_6

status: PASS tags: reset_test Derived: RESULT_RESET_6 Source: SPEC_RESET

Verify that the safety aspects of the Reset block are documented in the safety manual.

2.14.4 Test results

ID	Tags	Status
TEST_RESET_1	reset_test	PASS
TEST_RESET_2	reset_test	PASS
TEST_RESET_3	reset_test	PASS
TEST_RESET_4	reset_test	PASS
TEST_RESET_5	reset_test	PASS
TEST_RESET_6	reset_test	PASS

2.16 Constants (1/0)

Constant requirements flow diagram

Market requirement: Function block: Constant MREQ_BLOCK_CONSTANT

status: PASS tags: mreq, block, constant Derived: SPEC_BLOCK_CONSTANT

There shall exist a GUI function block that allows the user to configure a constant signal block. This function is useful for providing constant values as inputs to other blocks.

Specification: Function block: Constant SPEC_BLOCK_CONSTANT

status: PASS tags: spec, block, constant Derived: TEST_CONSTANT_1, TEST_CONSTANT_2, TEST_CONSTANT_3, TEST_CONSTANT_4 Source: MREQ_BLOCK_CONSTANT

The Constant block shall provide a constant value of logical 1 or 0. The Constant block shall have one output. Inputs None Outputs “1”: Outputs a constant value of 1. “0”: Outputs a constant value of 0. Properties None Underlying Compiler Blocks

2.16.2 Module tests

TEST: Test compiling with 1 as input TEST_CONSTANT_1

status: PASS tags: constant_test Derived: RESULT_CONSTANT_1 Source: SPEC_BLOCK_CONSTANT

Test specification Compile a Constant block with the value 1. Pass Criteria Verify that the generated SL3 code contains a constant function with the value 1. Verify that the constant value 1 is correctly placed in the list of inputs to another block. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Test compiling with 0 as input TEST_CONSTANT_2

status: PASS tags: constant_test Derived: RESULT_CONSTANT_2 Source: SPEC_BLOCK_CONSTANT

Test specification Compile a Constant block with the value 0. Pass Criteria Verify that the generated SL3 code contains a constant function with the value 0. Verify that the constant value 0 is correctly placed in the list of inputs to another block. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.16.3 Integration tests

TEST: Verify Constant block function TEST_CONSTANT_3

status: PASS tags: constant_test Derived: RESULT_CONSTANT_3 Source: SPEC_BLOCK_CONSTANT

Preconditions Compile a Constant block with a Single Output block connected to the output. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output signal is correctly set to logical 1 if the input is set to logical 1. Verify that the output signal is correctly set to logical 0 if the input is set to logical 0.

TEST: Constant in safety manual TEST_CONSTANT_4

status: PASS tags: constant_test Derived: RESULT_CONSTANT_4 Source: SPEC_BLOCK_CONSTANT

Verify that the safety aspects of the Constant block are documented in the safety manual.

2.16.4 Test results

ID	Tags	Status
TEST_CONSTANT_1	constant_test	PASS
TEST_CONSTANT_2	constant_test	PASS
TEST_CONSTANT_3	constant_test	PASS
TEST_CONSTANT_4	constant_test	PASS

2.17 Filter

Filter requirements flow diagram

Market requirement: Function block: Filter MREQ_GUI_FILTER

status: PASS tags: mreq, block, filter Derived: HAZARD_GUI_FILTER_01

A Filter function block shall be available to users in Simplifier Manager.

Hazard: Function block: Filter HAZARD_GUI_FILTER_01

status: PASS tags: hazard, block, filter Derived: SPEC_GUI_FILTER Source: MREQ_GUI_FILTER

Safety relies on the “DelayOFF” and “DelayON” inputs of the Filter to delay the output signal. If the “DelayOFF” and “DelayON” inputs are not functioning correctly, the output may not be delayed, which could lead to an unsafe function.

Specification: Function block: Filter SPEC_GUI_FILTER

status: PASS tags: spec, block, filter Derived: TEST_FILTER_1, TEST_FILTER_2, TEST_FILTER_3, TEST_FILTER_4, TEST_FILTER_5 Source: HAZARD_GUI_FILTER_01

The Filter block performs a general filter function: The Filter function block shall delay the input signal based on the specified DelayON and DelayOFF times. Inputs “Input”: Corresponds to the compiler input “input”. Outputs “Output”: Corresponds to the compiler output “output”. Properties DelayOFF: Corresponds to the compiler parameter t_off. DelayON: Corresponds to the compiler parameter t_on. State Diagram stateDiagram-v2 Start --> OFF OFF --> ON: input = 1 ON --> OFF: Input = 0 state ON { HIGH --> LOW: time > t_off LOW --> HIGH: time > t_on }

2.17.2 Module tests

TEST: Filter sl3 code review TEST_FILTER_1

status: PASS tags: filter_test Derived: RESULT_FILTER_1 Source: SPEC_GUI_FILTER

Preconditions Compile a Filter block with the following properties: DelayOFF = 100 DelayON = 200 Procedure Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Filter sl3 code review, max values TEST_FILTER_2

status: PASS tags: filter_test Derived: RESULT_FILTER_2 Source: SPEC_GUI_FILTER

Preconditions Compile a Filter block with the following properties: DelayOFF = 10000 DelayON = 10000 Procedure Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Filter sl3 code review, min values TEST_FILTER_3

status: PASS tags: filter_test Derived: RESULT_FILTER_3 Source: SPEC_GUI_FILTER

Preconditions Compile a Filter block with the following properties: DelayOFF = 0 DelayON = 0 Procedure Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.17.3 Integration tests

TEST: Verify the Filter function TEST_FILTER_4

status: PASS tags: filter_test Derived: RESULT_FILTER_4 Source: SPEC_GUI_FILTER

Preconditions Compile a Filter block with a Single Input connected to the input, a Single Output connected to the output and the following properties: DelayOFF = 100 DelayON = 200 Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the input and output signals are OFF/LOW/0V. Apply a HIGH signal to the input. Verify that the output turns on after the specified DelayON time. Apply a LOW signal to the input. Verify that the output turns off after the specified DelayOFF time. When the output is high, apply a pulse signal < 100ms to the input and verify that the output does not change state. When the output is low, apply a pulse signal < 200ms to the input and verify that the output does not change state.

TEST: Filter in safety manual TEST_FILTER_5

status: PASS tags: filter_test Derived: RESULT_FILTER_5 Source: SPEC_GUI_FILTER

Verify that the safety aspects of the Filter block are documented in the safety manual.

2.17.4 Test results

ID	Tags	Status
RESULT_FILTER_1	result; block; filter_test	PASS
RESULT_FILTER_2	result; block; filter_test	PASS
RESULT_FILTER_3	result; block; filter_test	PASS
RESULT_FILTER_4	result; block; filter_test	PASS
RESULT_FILTER_5	result; block; filter_test	PASS

2.19 Switch-on Filter

Switch-on Filter requirements flow diagram

Market requirement: Function block: Switch-on Filter MREQ_BLOCK_SWITCH_ON_FILTER

status: PASS tags: mreq, block, switch_on_filter Derived: SPEC_BLOCK_SWITCH_ON_FILTER

A Switch-on Filter function block shall be available to users in Simplifier Manager.

Specification: Function block: Switch-on Filter SPEC_BLOCK_SWITCH_ON_FILTER

status: PASS tags: spec, block, switch_on_filter Derived: TEST_SWITCH_ON_FILTER_1, TEST_SWITCH_ON_FILTER_2, TEST_SWITCH_ON_FILTER_3, TEST_SWITCH_ON_FILTER_4 Source: MREQ_BLOCK_SWITCH_ON_FILTER

The Switch-on Filter block adds a specified delay time before a high flank input signal is passed to the output. The Switch-on Filter function block shall delay the input signal based on the specified Filter time. Inputs “Input”: Corresponds to the compiler input “input”. Outputs “Output”: Corresponds to the compiler output “output”. Properties Filter time (ms): Corresponds to the compiler parameter t_on. Underlying Compiler Blocks

2.19.2 Module tests

TEST: Switch-on Filter sl3 code review TEST_SWITCH_ON_FILTER_1

status: PASS tags: switch_on_filter_test Derived: RESULT_SWITCH_ON_FILTER_1 Source: SPEC_BLOCK_SWITCH_ON_FILTER

Preconditions Compile a Switch-on Filter block with the following properties: Filter time (ms) = 100 Procedure Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Switch-on Filter sl3 code review, max values TEST_SWITCH_ON_FILTER_2

status: PASS tags: switch_on_filter_test Derived: RESULT_SWITCH_ON_FILTER_2 Source: SPEC_BLOCK_SWITCH_ON_FILTER

Preconditions Compile a Switch-on Filter block with the following properties: Filter time (ms) = 36000000 Procedure Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.19.3 Integration tests

TEST: Verify Switch-on Filter function TEST_SWITCH_ON_FILTER_3

status: PASS tags: switch_on_filter_test Derived: RESULT_SWITCH_ON_FILTER_3 Source: SPEC_BLOCK_SWITCH_ON_FILTER

Preconditions Compile a Switch-on Filter with a Single Input block connected to the input and a Single Output block connected to the output. Set the Filter time to 100ms. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the output is LOW/OFF/0V. Give a high signal on the input and verify that the output is delayed by 100ms. Give a pulse signal < 100ms to the input and verify that the output does not change state.

TEST: Switch-on Filter in manual TEST_SWITCH_ON_FILTER_4

status: PASS tags: switch_on_filter_test Derived: RESULT_SWITCH_ON_FILTER_4 Source: SPEC_BLOCK_SWITCH_ON_FILTER

Verify that the Switch-on Filter block is documented in the user manual.

2.19.4 Test results

ID	Tags	Status
TEST_SWITCH_ON_FILTER_1	switch_on_filter_test	PASS
TEST_SWITCH_ON_FILTER_2	switch_on_filter_test	PASS
TEST_SWITCH_ON_FILTER_3	switch_on_filter_test	PASS
TEST_SWITCH_ON_FILTER_4	switch_on_filter_test	PASS

2.20 Switch-off Filter

Filter requirements flow diagram

Market requirement: Function block: Switch-off Filter MREQ_BLOCK_SWITCH_OFF_FILTER

status: PASS tags: mreq, block, switch_off_filter Derived: SPEC_BLOCK_SWITCH_OFF_FILTER

A Switch-off Filter function block shall be available to users in Simplifier Manager.

Specification: Function block: Switch-off Filter SPEC_BLOCK_SWITCH_OFF_FILTER

status: PASS tags: spec, block, switch_off_filter Derived: TEST_SWITCH_OFF_FILTER_1, TEST_SWITCH_OFF_FILTER_2, TEST_SWITCH_OFF_FILTER_3, TEST_SWITCH_OFF_FILTER_4 Source: MREQ_BLOCK_SWITCH_OFF_FILTER

The Switch-off Filter block adds a specified delay time before a low flank input signal is passed to the output. The Switch-off Filter function block shall delay the input signal based on the specified Filter time. Inputs “Input”: Corresponds to the compiler input “input”. Outputs “Output”: Corresponds to the compiler output “output”. Properties Filter time (ms): Corresponds to the compiler parameter t_off. Underlying Compiler Blocks

2.20.2 Module tests

TEST: Compile a switch-off filter and observe the generated SL3 code with the specified properties TEST_SWITCH_OFF_FILTER_1

status: PASS tags: switch_off_filter_test Derived: RESULT_SWITCH_OFF_FILTER_1 Source: SPEC_BLOCK_SWITCH_OFF_FILTER

Test specification Compile a Switch-off Filter block with the following properties: Filter time (ms) = 100 Pass Criteria Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

TEST: Compile a switch-off filter and observe the generated SL3 code with the specified properties TEST_SWITCH_OFF_FILTER_2

status: PASS tags: switch_off_filter_test Derived: RESULT_SWITCH_OFF_FILTER_2 Source: SPEC_BLOCK_SWITCH_OFF_FILTER

Test specification Compile a Switch-off Filter block with the following properties: Filter time (ms) = 36000000 Pass Criteria Verify that the generated SL3 code contains the specified properties with the correct values appended to the arguments of the delay function. Verify that all input signals to the block are in the correct place in the SL3 output. Verify that all attributes (constant values) are named correctly and have the correct value in the SL3 output. Verify that any other block-specific logic is correct (such as inputs/outputs, memories, or other SL3 parameters).

2.20.3 Integration tests

TEST: Verify Switch-off Filter function TEST_SWITCH_OFF_FILTER_3

status: PASS tags: switch_off_filter_test Derived: RESULT_SWITCH_OFF_FILTER_3 Source: SPEC_BLOCK_SWITCH_OFF_FILTER

Preconditions Compile a Switch-off Filter with a Single Input block connected to the input and a Single Output block connected to the output. Set the Filter time to 100ms. Download to a single unit and measure all inputs and outputs with an oscilloscope or logic analyzer. Procedure Verify that the input signal is LOW/OFF/0V. Apply a HIGH signal to the input and verify that the output matches the input. Apply a LOW signal to the input and verify that the output is delayed by 100ms.

TEST: Switch-off Filter in safety manual TEST_SWITCH_OFF_FILTER_4

status: PASS tags: switch_off_filter_test Derived: RESULT_SWITCH_OFF_FILTER_4 Source: SPEC_BLOCK_SWITCH_OFF_FILTER

Verify that the safety aspects of the Switch-off Filter block are documented in the safety manual.

2.20.4 Test results

ID	Tags	Status
TEST_SWITCH_OFF_FILTER_1	switch_off_filter_test	PASS
TEST_SWITCH_OFF_FILTER_2	switch_off_filter_test	PASS
TEST_SWITCH_OFF_FILTER_3	switch_off_filter_test	PASS
TEST_SWITCH_OFF_FILTER_4	switch_off_filter_test	PASS

Compiler function blocks

3.1 dig_input

There shall exist a compiler function that evaluates the state of a digital input pin by comparing the input voltage to relative or absolute thresholds.

3.1.1 Requirement specification

• The dig_input function shall evaluate the state of a digital input pin by comparing the input voltage to some thresholds.

• The output (source) shall be 1 if the voltage on the specified pin is above the specified upper threshold, and 0 if below the specified lower threshold.

• The output shall keep its current value if the voltage is between the two thresholds (hysteresis).

• The thresholds shall be optionally specified as either percentages of the current power supply voltage, or specific voltages in millivolt (mV).

• If no specific thresholds are specified, the default thresholds shall be 25% and 75% of the current power supply voltage.

• It shall be possible to specify that the output is inverted, i.e., 1 if below the lower threshold, and 0 if above the upper threshold.

Inputs

None

Outputs

• source: 1 or 0, the state of the evaluated pin.

Parameters

• pin [1-14]: Which pin to evaluate.

• safe: If true, calculate result in both CPUs and synchronize it (AND with other CPU result) before logic.

• invert: Invert the result (above threshold = 0, below = 1).

• params.inp_threshold_rel_lo [0-1]: Powersupply relative threshold low. Default = 0.25.

• params.inp_threshold_rel_hi [0-1]: Powersupply relative threshold high. Default = 0.75.

• params.inp_threshold_abs_lo [0-33000]: Specifies an absolute voltage threshold in millivolt.

• params.inp_threshold_abs_hi [0-33000]: Specifies an absolute voltage threshold in millivolt.

Note that the params.* parameters are optional. If not specified, the default relative thresholds low = PSU*0.25, high = PSU*0.75 are used.

Syntax examples

A safe digital input on pin 6 with the default thresholds:

my_pin6_input:
   typ: dig_input
   pin: 6
   safe: true

A safe digital input on pin 14 with specific absolute thresholds:

my_pin14_absolute:
   typ: dig_input
   pin: 14
   safe: true
   params:
      inp_threshold_abs_lo: 2000 # 2V
      inp_threshold_abs_hi: 10000 # 10V

An inverted input on pin 1:

my_inverted_input:
   typ: dig_input
   pin: 1
   invert: true

3.1.2 Module tests

Test result summary

ID	Tags	Status
TEST_CFB_DIG_INPUT_1	dig_input	PASS
TEST_CFB_DIG_INPUT_2	dig_input	PASS
TEST_CFB_DIG_INPUT_3	dig_input	PASS
TEST_CFB_DIG_INPUT_4	dig_input	PASS
TEST_CFB_DIG_INPUT_5	dig_input	PASS

TEST: dig_input: code review 1 TEST_CFB_DIG_INPUT_1

status: PASS tags: dig_input Derived: RESULT_CFB_DIG_INPUT_1

Compile the following logic: io: my_input: typ: dig_input pin: 1 safe: true logic: - var.latchtoggle_2 = latch_tog(input=io.my_input.source, reset=0) In both CPUs, assert that: Pin 1 is used in all versions of the ftick_input_handling function, the low threshold is 25% of power supply voltage, the high threshold is 75% of power supply voltage, the output is synchronized between both CPUs (AND-ed with result from other CPU), the synchronized signal is used as the input to the toggle latch.

TEST: dig_input: code review 2 TEST_CFB_DIG_INPUT_2

status: PASS tags: dig_input Derived: RESULT_CFB_DIG_INPUT_2

Compile the following logic: io: my_input: typ: dig_input pin: 14 safe: true params: inp_threshold_abs_lo: 1234 inp_threshold_abs_hi: 5678 In both CPUs, assert that: the low threshold is 1234mV, the high threshold is 5678mV.

TEST: dig_input: code review 3 TEST_CFB_DIG_INPUT_3

status: PASS tags: dig_input Derived: RESULT_CFB_DIG_INPUT_3

Compile the following logic: io: my_input: typ: dig_input pin: 1 safe: true invert: true In both CPUs, assert that: the “source” output is inverted.

TEST: dig_input: code review 4 TEST_CFB_DIG_INPUT_4

status: PASS tags: dig_input Derived: RESULT_CFB_DIG_INPUT_4

Compile the following logic: io: my_input: typ: dig_input pin: 1 safe: true params: inp_threshold_rel_lo: 0.1 inp_threshold_rel_hi: 0.9 In both CPUs, assert that: the low threshold is 10% of power supply voltage, the high threshold is 90% of power supply voltage.

TEST: dig_input: code review 5 TEST_CFB_DIG_INPUT_5

status: PASS tags: dig_input Derived: RESULT_CFB_DIG_INPUT_5

Compile the following logic: io: my_input: typ: dig_input pin: 5 safe: false logic: - var.latchtoggle_2 = latch_tog(input=io.my_input.source, reset=0) Assert that: code for the function is only generated in CPU1, the source output signal is not available in CPU2, the toggle latch function is only generated in CPU1.

3.3 ossd

• The ossd block shall be able to control an output safety IO based on a binary control signal.

• When driving the output high, both CPUs shall measure that the voltage on the pin is within the specified limits.

(Since CPU1 ADC value is reduced when an output is driven high, CPU1 can only check that the voltage is above a lower value).

• When the output is high, CPU2 shall check that the voltage is within 90-110% of the current power supply voltage.

Inputs

• “ctrl”: Controls the output 1=ON, 0=OFF.

Outputs

None.

Parameters

• pin [1-14]: Which pin to control.

• safe: If true, both CPUs verify the outp_check_rel/outp_check_abs_mv maximum voltage.

• invert: The output is inverted relative to the ctrl input.

• params.outp_check_rel [0-1]: if not driving output high, the output measured voltage must be below this to be OK. Default = 0.5.

• params.outp_check_abs_mv [0-33000]: Powersupply relative threshold high. Default = 0. If != 0, takes precedence over outp_check_rel.

Syntax

Example of a digital output on pin 14:

my_pin_14:
   typ: ossd
   pin: 14
   safe: true
   invert: true

Example of a digital output on pin 6 with specific absolute threshold:

my_pin_6:
   typ: ossd
   pin: 6
   safe: true
   params:
      outp_check_abs_mv: 2000 # 2V

3.2.2 Module tests

Test result summary

ID	Tags	Status
TEST_CFB_OSSD_1	fblock_ossd	PASS
TEST_CFB_OSSD_2	fblock_ossd	PASS
TEST_CFB_OSSD_3	fblock_ossd	PASS

TEST: ossd: code review 1 TEST_CFB_OSSD_1

status: PASS tags: fblock_ossd Derived: RESULT_CFB_OSSD_1 Source: SWSREQ_019A, SWSREQ_022A

Compile the following logic: io: my_output: typ: ossd pin: 14 safe: true logic: - var.sqr = sqrwave(ctrl=1) | t_on = 100, t_off = 100 copies: - io.my_output.ctrl = var.sqr In both CPUs, assert that: In all versions of the ftick_input_handling function, the correct switch case and ADC value is used to read the voltage on pin 14, the output is controlled by the output from the square wave, when the output is low, the voltage is compared to 50% of the power supply voltage, if the voltage is above the threshold, an error is set, when the output is high, in CPU2, the voltage is within 90% and 110% of the power supply voltage. when the output is high, in CPU1, the voltage is above 20% of the power supply voltage. The output turns off in the ftick before measuring the OSSD voltage, and turns on again after being measured.

TEST: ossd: code review 2 TEST_CFB_OSSD_2

status: PASS tags: fblock_ossd Derived: RESULT_CFB_OSSD_2 Source: SWSREQ_019A, SWSREQ_022A

Compile the following logic: io: my_output: typ: ossd pin: 1 safe: true logic: - var.sqr = sqrwave(ctrl=1) | t_on = 100, t_off = 100 copies: - io.my_output.ctrl = var.sqr In both CPUs, assert that: In all versions of the ftick_input_handling function, the correct switch case and ADC value is used to read the voltage on pin 1,

TEST: ossd: code review 3 TEST_CFB_OSSD_3

status: PASS tags: fblock_ossd Derived: RESULT_CFB_OSSD_3 Source: SWSREQ_019A, SWSREQ_022A

Compile the following logic: io: my_output: typ: ossd pin: 1 safe: true params: outp_check_abs_mv: 1234 logic: - var.sqr = sqrwave(ctrl=1) | t_on = 100, t_off = 100 copies: - io.my_output.ctrl = var.sqr In both CPUs, assert that: when the output is low, the voltage is compared to the absolute threshold of 1234mV.

3.14 combo

There shall exist a function block which can be used to read an input signal from a pin, and output an output signal on the same pin. This shall be achieved by switching the output off for a short period to read the status of the input, and then switching the output on again. The purpose of this function is to be able to determine the state of a push button input, while simultaneously lighting an LED lamp on the same pin.

3.14.1 Requirement specification

The combo_io shall be able to read an input signal on a pin, and output another output signal on the same pin. The pin acts as an output most of the time, but switches the output off for a short period to read the voltage on the pin, and then switches the output on again. The input signal is checked by both CPUs. Note that no filtering is performed in this function. This function is intended to be used with a filtering function.

Inputs

• ctrl: Control of the output signal.

Outputs

• source: Status of the input pin.

Parameters

• pin [1-14]: The pin to use for the input/output.

• safe: If true, calculate result in both CPUs and synchronize it (AND with other CPU result) before logic.

• invert: Invert the result (above threshold = 0, below = 1).

• params.inp_threshold_rel_lo [0-1]: Powersupply relative threshold low. Default = 0.25.

• params.inp_threshold_rel_hi [0-1]: Powersupply relative threshold high. Default = 0.75.

• params.inp_threshold_abs_lo [0-33000]: Specifies an absolute voltage threshold in millivolt.

• params.inp_threshold_abs_hi [0-33000]: Specifies an absolute voltage threshold in millivolt.

Syntax

The combo function uses the same schema as other digital input functions:

my_combo:
   typ: combo
   pin: 2
   safe: true

3.14.2 Module tests

Test result summary

ID	Tags	Status
TEST_CFB_COMBO_1	combo	PASS
TEST_CFB_COMBO_2	combo	PASS
TEST_CFB_COMBO_3	combo	PASS
TEST_CFB_COMBO_4	combo	PASS
TEST_CFB_COMBO_5	combo	PASS

TEST: combo: code review 1 TEST_CFB_COMBO_1

status: PASS tags: combo Derived: RESULT_CFB_COMBO_1 Source: SWSREQ_021A

Compile the following sl3 logic: io: my_combo: typ: combo pin: 7 safe: true In both CPUs, assert that: the correct pin is used in all versions of the ftick_input_handling function, the correct signal is assigned the value of the evaluation of the input (and used in logic), the function is in output mode until it’s time to read the status of the input, it is impossible for the function to incorrectly read its own output as the input.

TEST: combo: code review 2 TEST_CFB_COMBO_2

status: PASS tags: combo Derived: RESULT_CFB_COMBO_2

Compile the following sl3 logic: io: my_combo: typ: combo pin: 7 safe: true params: inp_threshold_abs_lo: 2000 # 2V inp_threshold_abs_hi: 10000 # 10V In both CPUs, assert that: the low threshold is 2V, the high threshold is 10V.

TEST: combo: code review 3 TEST_CFB_COMBO_3

status: PASS tags: combo Derived: RESULT_CFB_COMBO_3

Compile the following sl3 logic: io: my_combo: typ: combo pin: 7 safe: true invert: true In both CPUs, assert that: the result is inverted.

TEST: combo: code review 4 TEST_CFB_COMBO_4

status: PASS tags: combo Derived: RESULT_CFB_COMBO_4

Compile the following sl3 logic: io: my_combo: typ: combo pin: 7 params: inp_threshold_rel_lo: 0.1 inp_threshold_rel_hi: 0.9 In both CPUs, assert that: the low threshold is 10% of power supply voltage, the high threshold is 90% of power supply voltage.

TEST: combo: code review 5 TEST_CFB_COMBO_5

status: PASS tags: combo Derived: RESULT_CFB_COMBO_5

Compile the following sl3 logic: io: my_combo: typ: combo pin: 7 safe: false logic: - var.latchtoggle_2 = latch_tog(input=io.my_input.source, reset=0) In both CPUs, assert that: code for the function is only generated in CPU1, the source output signal is not available in CPU2, the toggle latch function is only generated in CPU1.

3.5 latch_sr

Specification: latch_sr CFB_LATCH_SR

status: PASS

Maps 1:1 to the GUI function block SR-Latch. See function specification in Function block: SR-latch (SPEC_BLOCK_SR_LATCH). Syntax: var.latchsr_1 = latch_sr(s=var.a, r=var.b)

3.5.2 Module tests

TEST: latch_sr: code review TEST_CFB_LATCH_SR_1

status: PASS tags: latch_sr Derived: RESULT_CFB_LATCH_SR_1

Test specification Compile the following SL3 code and review the generated c code: logic: - var.a = negate(i=0) - var.b = negate(i=0) - var.latchsr_1 = latch_sr(s=var.a, r=var.b) Pass criteria In both CPUs, assert that: The output is set to 1 when set is 1 and reset is 0. The output is set to 0 when reset is 1. The output retains its previous value when both set and reset are 0. The output is set to 0 when both set and reset are 1.

3.8 sync_inputs

The Sync Inputs function is equivalent to a standard input function, but uses internal signals instead of physical pins. This function can be used for synchronizing several input signals (for example when more than one two-hand device controls a function).

• The Sync Inputs function shall have configurable inputs between 2-16.

• The Sync Inputs function shall have an output that is 1 if the function is in the ON state.

• The Sync Inputs function shall have a startup_test parameter that determines the initial state at power on.

• The Sync Inputs function shall have debounce_on and debounce_off parameters to manage input signal stability.

• The Sync Inputs function shall have a req_all_zero parameter to ensure all inputs are 0 before transitioning to the ON state.

• The Sync Inputs function shall have a simultaneity parameter to manage the timing difference between inputs when transitioning from OFF to ON state.

3.8.1 Requirement specification

The Sync Inputs function block takes multiple inputs and produces one output based on the following rules:

Inputs

• Configurable between 2-16.

Outputs

• “output”: This output is 1 if the function is in the ON state.

Parameters

• startup_test [true/false]: If true, the function starts in the WAIT_FOR_OFF(OFF) state at the time of power on. If false, the function starts in the OFF state at the time of power on.

• debounce_on [0-10000ms]: The function will wait this time when an input goes to 1, before considering that input to be 1. If the input goes back to 0, the time is reset.

• debounce_off [0-10000ms]: The function will wait this time when an input goes from 1 to 0 before considering that input to be 0. If the input goes back to 1 before the given time, the time is reset.

• req_all_zero [0-10000ms]: The function requires all inputs to be 0 for at least this time before it can go to ON state again.

• simultaneity [0-10000ms]: When the function is going from OFF to ON state, the inputs can differ for at most this time. If they differ for more than this time, the function will go to ERROR state and require a new valid OFF state, before it can go to ON state again.

State Diagram

        stateDiagram-v2

   Start           --> ALL_ON: startup_test = false
   Start           --> WAIT_FOR_OFF: startup_test\n = true
   WAIT_FOR_OFF    --> OFF: All inputs = 0\n for t > req_all_zero
   WAIT_FOR_OFF    --> ERROR: Any input that has been 0\n goes to 1
   ALL_ON          --> ON: t > debounce_on
   ALL_ON          --> OFF: Any input = 0
   ON              --> WAIT_FOR_OFF: Any input = 0 for\n longer than\n debounce_off
   OFF             --> ALL_ON: All inputs = 1
   OFF             --> ERROR: Inputs differ\n for t > simultaneity
   ERROR           --> OFF: All inputs = 0\n for t > req_all_zero

   WAIT_FOR_OFF: WAIT_FOR_OFF\n (OFF)
   ALL_ON: ALL_ON\n (OFF)
   ON: ON\n "on" = 1
    

Syntax

The following is an example of a sync_inputs function block:

var.syncinputs_1 = sync_inputs(i=var.a,i=var.b) | req_zero_time=0, simultaneity=0, debounce_on=0, debounce_off=0, startup_test=False

3.8.2 Module tests

Test result summary

ID	Tags	Status
TEST_CFB_SYNC_INPUTS_1	sync_inputs	PASS
TEST_CFB_SYNC_INPUTS_2	sync_inputs	PASS
TEST_CFB_SYNC_INPUTS_3	sync_inputs	PASS
TEST_CFB_SYNC_INPUTS_4	sync_inputs	PASS

TEST: sync_inputs: code review TEST_CFB_SYNC_INPUTS_1

status: PASS tags: sync_inputs Derived: RESULT_CFB_SYNC_INPUTS_1

Test specification Compile the following SL3 code and review the generated c code: - var.syncinputs_1 = sync_inputs(i=var.a,i=var.b) | req_zero_time=0, simultaneity=0, debounce_on=0, debounce_off=0, startup_test=False Pass criteria The generated c code shall contain a sync_inputs function with the correct inputs and outputs, and the signals var.myvar should be used in the correct place.

TEST: req_zero_time = 0, simultaneity = 0, debounce_on = 0, debounce_off = 0, startup_test = True TEST_CFB_SYNC_INPUTS_2

status: PASS tags: sync_inputs Derived: RESULT_CFB_SYNC_INPUTS_2

Test specification Compile the following SL3 code and review the generated c code: - var.syncinputs_1 = sync_inputs(i=var.a,i=var.b) | req_zero_time=0, simultaneity=0, debounce_on=0, debounce_off=0, startup_test=True Pass criteria The generated c code shall contain a sync_inputs function with a req_zero_time of 0, simultaneity of 0, debounce_on of 0, debounce_off of 0 and a startup_test of True.

TEST: req_zero_time = 10000, simultaneity = 10000, debounce_on = 10000, debounce_off = 10000, startup_test = True TEST_CFB_SYNC_INPUTS_3

status: PASS tags: sync_inputs Derived: RESULT_CFB_SYNC_INPUTS_3

Test specification Compile the following SL3 code and review the generated c code: - var.syncinputs_1 = sync_inputs(i=var.a,i=var.b) | req_zero_time=10000, simultaneity=10000, debounce_on=10000, debounce_off=10000, startup_test=True Pass criteria The generated c code shall contain a sync_inputs function with a req_zero_time of 10000, simultaneity of 10000, debounce_on of 10000, debounce_off of 10000 and a startup_test of True.

TEST: req_zero_time = 1, simultaneity = 2, debounce_on = 3, debounce_off = 4, startup_test = False TEST_CFB_SYNC_INPUTS_4

status: PASS tags: sync_inputs Derived: RESULT_CFB_SYNC_INPUTS_4

Test specification Compile the following SL3 code and review the generated c code: - var.syncinputs_1 = sync_inputs(i=var.a,i=var.b) | req_zero_time=1, simultaneity=2, debounce_on=3, debounce_off=4, startup_test=False Pass criteria The generated c code shall contain a sync_inputs function with a req_zero_time of 1, simultaneity of 2, debounce_on of 3, debounce_off of 4 and a startup_test of False.

Test results

To read these results refer to the test results of FSD124: FSD124v10 results

ID	Tags	Status
RESULT_CFB_COMBO_1	result; block; combo	PASS
RESULT_CFB_COMBO_2	result; block; combo	PASS
RESULT_CFB_COMBO_3	result; block; combo	PASS
RESULT_CFB_COMBO_4	result; block; combo	PASS
RESULT_CFB_COMBO_5	result; block; combo	PASS
RESULT_CONSTANT_1	result; block; constant_test	PASS
RESULT_CONSTANT_2	result; block; constant_test	PASS
RESULT_CONSTANT_3	result; block; constant_test	PASS
RESULT_CONSTANT_4	result; block; constant_test	PASS
RESULT_D_LATCH_1	result; block; d_latch_test	PASS
RESULT_D_LATCH_2	result; block; d_latch_test	PASS
RESULT_D_LATCH_3	result; block; d_latch_test	PASS
RESULT_CFB_DIG_INPUT_1	result; block; dig_input	PASS
RESULT_CFB_DIG_INPUT_2	result; block; dig_input	PASS
RESULT_CFB_DIG_INPUT_3	result; block; dig_input	PASS
RESULT_CFB_DIG_INPUT_4	result; block; dig_input	PASS
RESULT_CFB_DIG_INPUT_5	result; block; dig_input	PASS
RESULT_CFB_OSSD_1	result; block; fblock_ossd	PASS
RESULT_CFB_OSSD_2	result; block; fblock_ossd	PASS
RESULT_CFB_OSSD_3	result; block; fblock_ossd	PASS
RESULT_FILTER_1	result; block; filter_test	PASS
RESULT_FILTER_2	result; block; filter_test	PASS
RESULT_FILTER_3	result; block; filter_test	PASS
RESULT_FILTER_4	result; block; filter_test	PASS
RESULT_FILTER_5	result; block; filter_test	PASS
RESULT_GATE_1	result; block; gate_test	PASS
RESULT_GATE_2	result; block; gate_test	PASS
RESULT_GATE_3	result; block; gate_test	PASS
RESULT_GATE_4	result; block; gate_test	PASS
RESULT_GATE_5	result; block; gate_test	PASS
RESULT_GATE_6	result; block; gate_test	PASS
RESULT_GATE_7	result; block; gate_test	PASS
RESULT_GATE_8	result; block; gate_test	PASS
RESULT_GATE_9	result; block; gate_test	PASS
RESULT_GATE_10	result; block; gate_test	PASS
RESULT_GATE_11	result; block; gate_test	PASS
RESULT_GATE_12	result; block; gate_test	PASS
RESULT_GATE_13	result; block; gate_test	PASS
RESULT_CFB_LATCH_SR_1	result; block; latch_sr	PASS
RESULT_NOT_1	result; block; not_test	PASS
RESULT_NOT_2	result; block; not_test	PASS
RESULT_NOT_3	result; block; not_test	PASS
RESULT_RESET_1	result; block; reset_test	PASS
RESULT_RESET_2	result; block; reset_test	PASS
RESULT_RESET_3	result; block; reset_test	PASS
RESULT_RESET_4	result; block; reset_test	PASS
RESULT_RESET_5	result; block; reset_test	PASS
RESULT_RESET_6	result; block; reset_test	PASS
RESULT_SINGLE_INPUT_1	result; block; single_input_test	PASS
RESULT_SINGLE_INPUT_2	result; block; single_input_test	PASS
RESULT_SINGLE_INPUT_3	result; block; single_input_test	PASS
RESULT_SINGLE_OUTPUT_1	result; block; single_output_test	PASS
RESULT_SINGLE_OUTPUT_2	result; block; single_output_test	PASS
RESULT_SINGLE_OUTPUT_3	result; block; single_output_test	PASS
RESULT_SQUARE_WAVE_1	result; block; sqrwave_test	PASS
RESULT_SQUARE_WAVE_2	result; block; sqrwave_test	PASS
RESULT_SQUARE_WAVE_3	result; block; sqrwave_test	PASS
RESULT_SQUARE_WAVE_4	result; block; sqrwave_test	PASS
RESULT_SQUARE_WAVE_5	result; block; sqrwave_test	PASS
RESULT_SR_LATCH_1	result; block; sr_latch_test	PASS
RESULT_SR_LATCH_2	result; block; sr_latch_test	PASS
RESULT_SR_LATCH_3	result; block; sr_latch_test	PASS
RESULT_SWITCH_OFF_FILTER_1	result; block; switch_off_filter_test	PASS
RESULT_SWITCH_OFF_FILTER_2	result; block; switch_off_filter_test	PASS
RESULT_SWITCH_OFF_FILTER_3	result; block; switch_off_filter_test	PASS
RESULT_SWITCH_OFF_FILTER_4	result; block; switch_off_filter_test	PASS
RESULT_SWITCH_ON_FILTER_1	result; block; switch_on_filter_test	PASS
RESULT_SWITCH_ON_FILTER_2	result; block; switch_on_filter_test	PASS
RESULT_SWITCH_ON_FILTER_3	result; block; switch_on_filter_test	PASS
RESULT_SWITCH_ON_FILTER_4	result; block; switch_on_filter_test	PASS
RESULT_CFB_SYNC_INPUTS_1	result; block; sync_inputs	PASS
RESULT_CFB_SYNC_INPUTS_2	result; block; sync_inputs	PASS
RESULT_CFB_SYNC_INPUTS_3	result; block; sync_inputs	PASS
RESULT_CFB_SYNC_INPUTS_4	result; block; sync_inputs	PASS
RESULT_T_LATCH_1	result; block; t_latch_test	PASS
RESULT_T_LATCH_2	result; block; t_latch_test	PASS
RESULT_T_LATCH_3	result; block; t_latch_test	PASS

RESULT: Single Input sl3 code review RESULT_SINGLE_INPUT_1

status: PASS tags: result, block, single_input_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_INPUT_1

RESULT: Verify Single Input function RESULT_SINGLE_INPUT_2

status: PASS tags: result, block, single_input_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_INPUT_2

RESULT: Single Input in safety manual RESULT_SINGLE_INPUT_3

status: PASS tags: result, block, single_input_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_INPUT_3

RESULT: Single Output sl3 code review RESULT_SINGLE_OUTPUT_1

status: PASS tags: result, block, single_output_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_OUTPUT_1, SWSREQ_019A

RESULT: Verify Single Output function RESULT_SINGLE_OUTPUT_2

status: PASS tags: result, block, single_output_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_OUTPUT_2

RESULT: Single Output in safety manual RESULT_SINGLE_OUTPUT_3

status: PASS tags: result, block, single_output_test date: 2025-08-04 owner: WF Source: TEST_SINGLE_OUTPUT_3

RESULT: AND Gate sl3 code review RESULT_GATE_1

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_1

RESULT: NAND Gate sl3 code review RESULT_GATE_2

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_2

RESULT: OR Gate sl3 code review RESULT_GATE_3

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_3

RESULT: NOR Gate sl3 code review RESULT_GATE_4

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_4

RESULT: XOR Gate sl3 code review RESULT_GATE_5

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_5

RESULT: XNOR Gate sl3 code review RESULT_GATE_6

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_6

RESULT: Verify AND Gate function RESULT_GATE_7

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_7

RESULT: Verify NAND Gate function RESULT_GATE_8

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_8

RESULT: Verify OR Gate function RESULT_GATE_9

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_9

RESULT: Verify NOR Gate function RESULT_GATE_10

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_10

RESULT: Verify XOR Gate function RESULT_GATE_11

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_11

RESULT: Verify XNOR Gate function RESULT_GATE_12

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_12

RESULT: Gate in safety manual RESULT_GATE_13

status: PASS tags: result, block, gate_test date: 2025-08-04 owner: WF Source: TEST_GATE_13

RESULT: NOT sl3 code review RESULT_NOT_1

status: PASS tags: result, block, not_test date: 2025-08-04 owner: WF Source: TEST_NOT_1

RESULT: Verify NOT block functionality with various inputs RESULT_NOT_2

status: PASS tags: result, block, not_test date: 2025-08-04 owner: WF Source: TEST_NOT_2

RESULT: NOT in safety manual RESULT_NOT_3

status: PASS tags: result, block, not_test date: 2025-08-04 owner: WF Source: TEST_NOT_3

RESULT: SR-Latch sl3 code review RESULT_SR_LATCH_1

status: PASS tags: result, block, sr_latch_test date: 2025-08-04 owner: WF Source: TEST_SR_LATCH_1

RESULT: Verify SR Latch function RESULT_SR_LATCH_2

status: PASS tags: result, block, sr_latch_test date: 2025-08-04 owner: WF Source: TEST_SR_LATCH_2

RESULT: SR-Latch in safety manual RESULT_SR_LATCH_3

status: PASS tags: result, block, sr_latch_test date: 2025-08-04 owner: WF Source: TEST_SR_LATCH_3

RESULT: T-Latch sl3 code review RESULT_T_LATCH_1

status: PASS tags: result, block, t_latch_test date: 2025-08-04 owner: WF Source: TEST_T_LATCH_1

RESULT: Verify T Latch function RESULT_T_LATCH_2

status: PASS tags: result, block, t_latch_test date: 2025-08-04 owner: WF Source: TEST_T_LATCH_2

RESULT: T-Latch in safety manual RESULT_T_LATCH_3

status: PASS tags: result, block, t_latch_test date: 2025-08-04 owner: WF Source: TEST_T_LATCH_3

RESULT: D-Latch sl3 code review RESULT_D_LATCH_1

status: PASS tags: result, block, d_latch_test date: 2025-08-04 owner: WF Source: TEST_D_LATCH_1

RESULT: Verify D Latch function RESULT_D_LATCH_2

status: PASS tags: result, block, d_latch_test date: 2025-08-04 owner: WF Source: TEST_D_LATCH_2

RESULT: D-Latch in safety manual RESULT_D_LATCH_3

status: PASS tags: result, block, d_latch_test date: 2025-08-04 owner: WF Source: TEST_D_LATCH_3

RESULT: Square wave sl3 code review RESULT_SQUARE_WAVE_1

status: PASS tags: result, block, sqrwave_test date: 2025-08-04 owner: WF Source: TEST_SQUARE_WAVE_1

RESULT: Square wave: Min values RESULT_SQUARE_WAVE_2

status: PASS tags: result, block, sqrwave_test date: 2025-08-04 owner: WF Source: TEST_SQUARE_WAVE_2

RESULT: Square wave: Max values RESULT_SQUARE_WAVE_3

status: PASS tags: result, block, sqrwave_test date: 2025-08-04 owner: WF Source: TEST_SQUARE_WAVE_3

RESULT: Verify Square Wave function RESULT_SQUARE_WAVE_4

status: PASS tags: result, block, sqrwave_test date: 2025-08-04 owner: WF Source: TEST_SQUARE_WAVE_4

RESULT: Square wave in safety manual RESULT_SQUARE_WAVE_5

status: PASS tags: result, block, sqrwave_test date: 2025-08-04 owner: WF Source: TEST_SQUARE_WAVE_5

RESULT: Reset: Minimum Push Time = 20 RESULT_RESET_1

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_1

RESULT: Reset: Minimum Push Time = 0 RESULT_RESET_2

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_2

RESULT: Reset: Minimum Push Time = 10000 RESULT_RESET_3

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_3

RESULT: Verify Reset function 1 RESULT_RESET_4

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_4

RESULT: Verify Reset function 2 RESULT_RESET_5

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_5

RESULT: Reset in safety manual RESULT_RESET_6

status: PASS tags: result, block, reset_test date: 2025-08-04 owner: WF Source: TEST_RESET_6

RESULT: Test compiling with 1 as input RESULT_CONSTANT_1

status: PASS tags: result, block, constant_test date: 2025-08-04 owner: WF Source: TEST_CONSTANT_1

RESULT: Test compiling with 0 as input RESULT_CONSTANT_2

status: PASS tags: result, block, constant_test date: 2025-08-04 owner: WF Source: TEST_CONSTANT_2

RESULT: Verify Constant block function RESULT_CONSTANT_3

status: PASS tags: result, block, constant_test date: 2025-08-04 owner: WF Source: TEST_CONSTANT_3

RESULT: Constant in safety manual RESULT_CONSTANT_4

status: PASS tags: result, block, constant_test date: 2025-08-04 owner: WF Source: TEST_CONSTANT_4

RESULT: Filter sl3 code review RESULT_FILTER_1

status: PASS tags: result, block, filter_test date: 2025-08-04 owner: WF Source: TEST_FILTER_1

RESULT: Filter sl3 code review, max values RESULT_FILTER_2

status: PASS tags: result, block, filter_test date: 2025-08-04 owner: WF Source: TEST_FILTER_2

RESULT: Filter sl3 code review, min values RESULT_FILTER_3

status: PASS tags: result, block, filter_test date: 2025-08-04 owner: WF Source: TEST_FILTER_3

RESULT: Verify the Filter function RESULT_FILTER_4

status: PASS tags: result, block, filter_test date: 2025-08-04 owner: WF Source: TEST_FILTER_4

RESULT: Filter in safety manual RESULT_FILTER_5

status: PASS tags: result, block, filter_test date: 2025-08-04 owner: WF Source: TEST_FILTER_5

RESULT: Switch-on Filter sl3 code review RESULT_SWITCH_ON_FILTER_1

status: PASS tags: result, block, switch_on_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_ON_FILTER_1

RESULT: Switch-on Filter sl3 code review, max values RESULT_SWITCH_ON_FILTER_2

status: PASS tags: result, block, switch_on_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_ON_FILTER_2

RESULT: Verify Switch-on Filter function RESULT_SWITCH_ON_FILTER_3

status: PASS tags: result, block, switch_on_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_ON_FILTER_3

RESULT: Switch-on Filter in manual RESULT_SWITCH_ON_FILTER_4

status: PASS tags: result, block, switch_on_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_ON_FILTER_4

RESULT: Compile a switch-off filter and observe the generated SL3 code with the specified properties RESULT_SWITCH_OFF_FILTER_1

status: PASS tags: result, block, switch_off_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_OFF_FILTER_1

RESULT: Compile a switch-off filter and observe the generated SL3 code with the specified properties RESULT_SWITCH_OFF_FILTER_2

status: PASS tags: result, block, switch_off_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_OFF_FILTER_2

RESULT: Verify Switch-off Filter function RESULT_SWITCH_OFF_FILTER_3

status: PASS tags: result, block, switch_off_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_OFF_FILTER_3

RESULT: Switch-off Filter in safety manual RESULT_SWITCH_OFF_FILTER_4

status: PASS tags: result, block, switch_off_filter_test date: 2025-08-04 owner: WF Source: TEST_SWITCH_OFF_FILTER_4

RESULT: latch_sr: code review RESULT_CFB_LATCH_SR_1

status: PASS tags: result, block, latch_sr date: 2025-08-04 owner: WF Source: TEST_CFB_LATCH_SR_1

RESULT: RESULT_CFB_SYNC_INPUTS_1 RESULT_CFB_SYNC_INPUTS_1

status: PASS tags: result, block, sync_inputs date: 2025-08-04 owner: WF Source: TEST_CFB_SYNC_INPUTS_1

RESULT: RESULT_CFB_SYNC_INPUTS_2 RESULT_CFB_SYNC_INPUTS_2

status: PASS tags: result, block, sync_inputs date: 2025-08-04 owner: WF Source: TEST_CFB_SYNC_INPUTS_2

RESULT: RESULT_CFB_SYNC_INPUTS_3 RESULT_CFB_SYNC_INPUTS_3

status: PASS tags: result, block, sync_inputs date: 2025-08-04 owner: WF Source: TEST_CFB_SYNC_INPUTS_3

RESULT: RESULT_CFB_SYNC_INPUTS_4 RESULT_CFB_SYNC_INPUTS_4

status: PASS tags: result, block, sync_inputs date: 2025-08-04 owner: WF Source: TEST_CFB_SYNC_INPUTS_4

RESULT: Sync inputs gui block 3 RESULT_GUI_SYNC_INPUTS_3

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_3

RESULT: Sync inputs gui block 4 RESULT_GUI_SYNC_INPUTS_4

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_4

RESULT: Sync inputs gui block 5 RESULT_GUI_SYNC_INPUTS_5

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_5

RESULT: Sync inputs gui block 6 RESULT_GUI_SYNC_INPUTS_6

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_6

RESULT: Sync inputs gui block 7 RESULT_GUI_SYNC_INPUTS_7

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_7

RESULT: Sync inputs gui block 8 RESULT_GUI_SYNC_INPUTS_8

status: PASS tags: fsd124 date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_8

RESULT: RESULT_CFB_DIG_INPUT_1 RESULT_CFB_DIG_INPUT_1

status: PASS tags: result, block, dig_input date: 2025-08-04 owner: WF Source: TEST_CFB_DIG_INPUT_1

RESULT: RESULT_CFB_DIG_INPUT_2 RESULT_CFB_DIG_INPUT_2

status: PASS tags: result, block, dig_input date: 2025-08-04 owner: WF Source: TEST_CFB_DIG_INPUT_2

RESULT: RESULT_CFB_DIG_INPUT_3 RESULT_CFB_DIG_INPUT_3

status: PASS tags: result, block, dig_input date: 2025-08-04 owner: WF Source: TEST_CFB_DIG_INPUT_3

RESULT: RESULT_CFB_DIG_INPUT_4 RESULT_CFB_DIG_INPUT_4

status: PASS tags: result, block, dig_input date: 2025-08-04 owner: WF Source: TEST_CFB_DIG_INPUT_4

RESULT: RESULT_CFB_DIG_INPUT_5 RESULT_CFB_DIG_INPUT_5

status: PASS tags: result, block, dig_input date: 2025-08-04 owner: WF Source: TEST_CFB_DIG_INPUT_5

RESULT: RESULT_GUI_SYNC_INPUTS_1 RESULT_GUI_SYNC_INPUTS_1

status: PASS tags: fsd124, sync_inputs_gui_module_tests date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_1

RESULT: RESULT_GUI_SYNC_INPUTS_2 RESULT_GUI_SYNC_INPUTS_2

status: PASS tags: fsd124, sync_inputs_gui_module_tests date: 2025-08-04 owner: WF Source: TEST_GUI_SYNC_INPUTS_2

RESULT: RESULT_CFB_OSSD_1 RESULT_CFB_OSSD_1

status: PASS tags: result, block, fblock_ossd date: 2025-08-04 owner: WF Source: TEST_CFB_OSSD_1

RESULT: RESULT_CFB_OSSD_2 RESULT_CFB_OSSD_2

status: PASS tags: result, block, fblock_ossd date: 2025-08-04 owner: WF Source: TEST_CFB_OSSD_2

RESULT: RESULT_CFB_OSSD_3 RESULT_CFB_OSSD_3

status: PASS tags: result, block, fblock_ossd date: 2025-08-04 owner: WF Source: TEST_CFB_OSSD_3

RESULT: RESULT_CFB_COMBO_1 RESULT_CFB_COMBO_1

status: PASS tags: result, block, combo date: 2025-08-04 owner: WF Source: TEST_CFB_COMBO_1

RESULT: RESULT_CFB_COMBO_2 RESULT_CFB_COMBO_2

status: PASS tags: result, block, combo date: 2025-08-04 owner: WF Source: TEST_CFB_COMBO_2

RESULT: RESULT_CFB_COMBO_3 RESULT_CFB_COMBO_3

status: PASS tags: result, block, combo date: 2025-08-04 owner: WF Source: TEST_CFB_COMBO_3

RESULT: RESULT_CFB_COMBO_4 RESULT_CFB_COMBO_4

status: PASS tags: result, block, combo date: 2025-08-04 owner: WF Source: TEST_CFB_COMBO_4

RESULT: RESULT_CFB_COMBO_5 RESULT_CFB_COMBO_5

status: PASS tags: result, block, combo date: 2025-08-04 owner: WF Source: TEST_CFB_COMBO_5

Motivations

Motivation: SWSREQ_008A MOTIVATION_124_001

status: PASS tags: fsd124 Source: SWSREQ_008A

The GUI software allows the user to create logic by using a block diagram language. See FSD124 test results.

Motivation: SWSREQ_009A MOTIVATION_124_002

status: PASS tags: fsd124 Source: SWSREQ_009A

This is achieved by changing the communication maximum timeouts, as well as by changing filtering parameters on inputs.

Motivation: SWSREQ_004A MOTIVATION_124_003

status: PASS tags: fsd124 Source: SWSREQ_004A, SWSREQ_005A

The GUI software allows the user to change the minimum and maximum power supply voltage in the node parameters.

Appendix

Sl3 template for module tests

Below is the template for module tests. Any test that does not specify all the logic uses this template:

nodes:
 - typ: standard
   node_idx: 0
   node_gui_nr: 1

   # io, memories, logic, copies go here.

   node_parameters:
      mem_groups_offset: 0
      mem_groups_num: 1
      display_connector_mode: DISPLAY

parameters:
   slottime_ms: 1
   silent_slottime_ms: 20
   radio_packet_type: small
   glb_mem_tmo:
      safe_area: 500
      unsafe_area: 500

Revision History

Date	By	Version	Description
2017-11-02	William Forsdal	V1	Initial version
2018-04-16	William Forsdal	V2	Add more blocks and tests
2018-06-08	William Forsdal	V5	updated blocks and tests (sync_inputs)
2018-10-10	William Forsdal	V6	Added more info to test results Added new tests to cover DREQs Added description of test equipment
2023-11-09	Orpheus Johansson	V7	Copied over old document to new structure.
2025-08-04	WF	V8	Updated tests to point to test.